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is43lr32800g, is46lr32800g 1 www.issi.com - dram@issi.com rev. a | november 2013 2m x 32bits x 4banks mobile ddr sdram description the is43/46lr32800g is 268,435,456 bits cmos mobile double data rate synchronous dram organized as 4 banks of 2,097,152 words x 32 bits. this product uses a double - data - rate architecture to achieve high - speed operation . the data input/ output signals are transmitted on a 32 - bit bus. the double data rate architecture is essentially a 2 n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. this product offer s fully synchronous operations referenced to both rising and falling edges of the clock. the data paths are internally pipelined and 2 n - bit s prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with lvcmos. features ? jedec standard 1.8v power supply. ? vdd = 1.8v , vddq = 1.8v ? four internal banks for concurrent operation ? mrs cycle with addr ess key programs - cas latency 2, 3 (clock) - burst length (2, 4, 8, 16) - burst type (sequential & interleave) ? fully differential clock inputs (ck, /ck) ? all inputs except data & dm are sampled at the rising edge of the system clock ? data i/o transaction on both edges of d ata strobe ? bidirectional data strobe per byte of data (dqs) ? dm for write masking only ? edge aligned data & data strobe output ? center aligned data & data strobe input ? 64 ms refresh period (4k cycle) ? auto & self refresh ? c oncurrent auto precharge ? maximum clock frequency up to 200mh z ? maximum data rate up to 400mbps/pin ? power saving support - pasr (partial array self refresh) - auto tcsr (temperature compensated self refresh) - deep power down mode - programmable driver strength control by full strength or 3/4, 1/2 , 1/4, 1/8 of full strength ? status register read (srr) ? lvcmos compatible inputs/outputs ? packages: - 90 - ball bga - 152 - ball pop bga copyright ? 2013 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and it s products at any time without notice. issi assumes no liability arising out of the application or use of any information, pr odu cts or services described herein. customers are advised to obtain the latest version of this device specification before relying on any publi she d information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fa ilu re or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives wri tte n assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances
is43lr32800g, is46lr32800g 2 rev. a | november 2013 www.issi.com - dram@issi.com figure 1: 90ball fbga ball assignment [top view] vss dq31 dq16 vdd vddq dq29 dq18 vssq vssq dq27 dq20 vddq vddq dq25 dq22 vssq vssq dqs3 dqs2 vddq vdd dm3 dm2 vss cke clk /cas /ras a9 a11 ba 0 ba1 a6 a7 a0 a1 a4 dm1 dm0 a3 vssq dqs1 dqs0 vddq vddq dq9 dq6 vssq vssq dq11 dq4 vddq vddq dq13 dq2 vssq vss dq15 dq0 vdd a 1 vddq dq17 dq19 dq21 dq23 nc /we /cs a10 a2 dq7 dq5 dq3 dq1 vddq vssq dq30 dq28 dq26 dq24 nc /clk nc a8 a5 dq8 dq10 dq12 dq14 vssq b c d e f g h j k l m p r n 2 3 4 5 6 7 8 9
is43lr32800g, is46lr32800g 3 rev. a | november 2013 www.issi.com - dram@issi.com figure 2: 152 - ball vfbga ball assignment notes: 1. although not bonded to the die, these pins may be connected on the package substrate. 2. a12 (r21) is used for 1gb (32mx32) and 512mb (16mx32 ), and is nc for 256mb (8mx32). [top view]
is43lr32800g, is46lr32800g 4 rev. a | november 2013 www.issi.com - dram@issi.com table2 : pin descriptions symbol type function descriptions ck, /ck input system clock the system clock input. ck and /ck are differential clock inputs. all address and control input signals are registered on the crossing of the rising edge of ck and falling edge of /ck. input and output data is referenced to the crossing of ck and /ck. cke input clock enable cke is clock enable controls input. cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. cke is synchronous for all functions except for self refresh exit, which is achieved asynchronously. /cs input chip select /cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when /cs is registered high. /cs provides for external bank selection on systems with multiple banks. /cs is considered part of the command code. ba0, ba1 input bank address ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also determine which mode register (standard mode register or extended mode register) is loaded during a load mode register command. a0~a11 input address row address : ra0~ra11 column address : ca0~ca8 auto precharge : a10 /ras, /cas, /we input row address strobe, column address strobe, write enable /ras, /cas and /we define the operation . refer function truth table for details . dm0~dm3 input data input mask dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm balls are input - only. dq0~dq31 in/output data input/output data input/output pin . dqs0~dqs3 in/output data input/output strobe output with read data, input with write data. dqs is edge - aligned with read data, centered in write data. data strobe is used to capture data. tq output temperature sensor tq goes high if tj > 85 ? c vdd supply power supply power supply vss supply ground ground vddq supply dq power supply power supply for dq vssq supply dq ground ground for dq nc nc no connection no connection.
is43lr32800g, is46lr32800g 5 rev. a | november 2013 www.issi.com - dram@issi.com figure 3 : functional block diagram extended mode register self refresh logic & timer internal row counter row pre decoder column pre decoder column add counter address register mode register data out control burst counter address buffers state machine row decoders row decoders row decoders row decoders 4 mx 32 bank 1 4 mx 32 bank 0 memory cell array column decoders 4 mx 32 bank 2 4 mx 32 bank 3 write data register 2 - bit prefetch unit sense amp&i/o gate output buffer & logic dq0 . . . . . . . dq 31 data strobe transmitter data strobe receiver input buffer & logic | | 32 | | | | 64 | | ds dqs0 ~ dqs3 ds x32 x64 pa sr row active refresh column active bank select burst length cas latency --------- a0 a1 a11 ba 0 ba 1 dm0 ~ dm3 /we /cas /ras /cs cke ck /ck temperature sensor tq
is43lr32800g, is46lr32800g 6 rev. a | november 2013 www.issi.com - dram@issi.com figure4 : simplified state diagram power o n precharge a ll b anks mrs emrs active p ower d own deep power down idle a ll b anks p recharged auto refresh row a ctive precharge preall write write a read read a burst s top precharge p ower d own dpds power a pplied dpdsx mrs refa act ckeh ckel refs refsx s elf r efresh pre ckel ckeh write read bst pre pre pre write a write read read a read write a read a automatic sequence act = active bst = burst ckel = enter power - down ckeh = exit power - down dpds = enter deep power - down dpdsx = exit deep power - down emrs = ext. mode reg. set mrs = mode register set pre = precharge preall= precharge all banks refa = auto refresh refs = enter self refresh refsx = exit self refresh read = read w/o auto precharge read a = read with auto precharge srr = status register read write = write w/o auto precharge write a = write with auto precharge srr mrs read
is43lr32800g, is46lr32800g 7 rev. a | november 2013 www.issi.com - dram@issi.com burst type accesses within a given burst may be programmed to be either sequential or interleaved ; this is referred to as the burst type and is selected via bit m 3 . the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 3 . m3 burst type 0 sequential 1 interleave m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved m2 m1 m0 burst length m3 = 0 m3 = 1 0 0 0 reserved reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 16 16 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved address bus a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 figure 5 : mode register set (mrs) definition ba0 ba1 14 13 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 cas latency bt burst length note: m14(ba1) = 0 and m13(ba0) = 0 to select mode register mode register (mx)
is43lr32800g, is46lr32800g 8 rev. a | november 2013 www.issi.com - dram@issi.com table3 : burst definition burst length starting column address order of access within a burst a3 a2 a1 a0 sequential mode interleave mode 2 x x x 0 0 - 1 0 - 1 x x x 1 1 - 0 1 - 0 4 x x 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 x x 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 x x 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 x x 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 8 x 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 x 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 x 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 x 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 x 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 x 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 x 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 x 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 16 0 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 0 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 - 9 - 8 - 11 - 10 - 13 - 12 - 15 - 14 0 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 - 10 - 11 - 8 - 9 - 14 - 15 - 12 - 13 0 0 1 1 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 - 11 - 10 - 9 - 8 - 15 - 14 - 13 - 12 0 1 0 0 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 - 12 - 13 - 14 - 15 - 8 - 9 - 10 - 11 0 1 0 1 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 - 13 - 12 - 15 - 14 - 9 - 8 - 11 - 10 0 1 1 0 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 - 14 - 15 - 12 - 13 - 10 - 11 - 8 - 9 0 1 1 1 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 1 0 0 0 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 1 0 0 1 9 - 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 9 - 8 - 11 - 10 - 13 - 12 - 15 - 14 - 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 1 0 1 0 10 - 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 10 - 11 - 8 - 9 - 14 - 15 - 12 - 13 - 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 1 0 1 1 11 - 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 11 - 10 - 9 - 8 - 15 - 14 - 13 - 12 - 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 1 0 0 12 - 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 12 - 13 - 14 - 15 - 8 - 9 - 10 - 11 - 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 1 0 1 13 - 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 13 - 12 - 15 - 14 - 9 - 8 - 11 - 10 - 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 1 0 14 - 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 14 - 15 - 12 - 13 - 10 - 11 - 8 - 9 - 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 1 15 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 note : 1 . for a burst length of two, a 1 - a 8 select the block of two burst ; a 0 selects the starting column within the block . 2 . for a burst length of four, a 2 - a 8 select the block of four burst ; a 0 - a 1 select the starting column within the block . 3 . for a burst length of eight, a 3 - a 8 select the block of eight burst ; a 0 - a 2 select the starting column within the block . 4 . for a burst length of sixteen, a 4 - a 8 select the block of eight burst ; a 0 - a 3 select the starting column within the block . 5 . whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block .
is43lr32800g, is46lr32800g 9 rev. a | november 2013 www.issi.com - dram@issi.com figure5 : extended mode set (emrs) register address bus extended mode register (ex) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 e2 e1 e0 self refresh coverage 0 0 0 four banks 0 0 1 two bank (ba1=0) 0 1 0 one bank (ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved 1 0 1 one eighth of total bank (ba1 = ba0 = row address msb=0) 1 1 0 one sixteenth of total bank (ba1 = ba0 = row address 2 msbs=0) 1 1 1 reserved e7 e6 e5 driver strength 0 0 0 full strength 0 0 1 1/2 strength 0 1 0 1/4 strength 0 1 1 1/8 strength 1 0 0 3/4 strength 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved ba0 ba1 14 13 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 ds 0 0 pasr note: 1. e14(ba1) = 1 and e13(ba0) = 0 to select extended mode register
is43lr32800g, is46lr32800g 10 rev. a | november 2013 www.issi.com - dram@issi.com the 256 mb mobile ddr sdram is a high - speed cmos, dynamic random - access memory containing 268 , 435 , 456 - bits . it is internally configured as a quad - bank dram . the 256 mb mobile ddr sdram uses a double data rate architecture to achieve high speed operation . the double data rate architecture is essentially a 2 n - prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o balls, single read or write access for the 256 mb mobile ddr sdram consists of a single 2 n - bit wide, one - clock - cycle data transfer at the internal dram core and two corresponding n - bit wide, one - half - clock - cycle data transfers at the i/o balls . read and write accesses to the mobile ddr sdram are burst oriented ; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence . accesses begin with the registration of an active command, which is then followed by a read or write command . the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba 0 , ba 1 select the bank ; a 0 C a 11 select the row) . the address bits registered coincident with the read or write command are used to select the starting column location for the burst access . it should be noted that the dll signal that is typically used on standard ddr devices is not necessary on the mobile ddr sdram . it has been omitted to save power . prior to normal operation, the mobile ddr sdram must be powered up and initialized . the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation . power up and initialization mobile ddr sdram must be powered up and initialized in a predefined manner . power must be applied to vdd and vddq (simultaneously) . after power up, an initial pause of 200 usec is required . and a precharge all command will be issued to the mobile ddr . then, 2 or more auto refresh cycles will be provided . after the auto refresh cycles are completed, a mode register set(mrs) command will be issued to program the specific mode of operation (cas latency, burst length, etc . ) and a extended mode register set(emrs) command will be issued to partial array self refresh(pasr) . the following these cycles, the mobile ddr sdram is ready for normal operation . to ensure device functionality, there is a predefined sequence that must occur at device power up or if there is any interruption of device power . to properly initialize the mobile ddr sdram, this sequence must be followed : 1 . to prevent device latch - up, it is recommended the core power (vdd) and i/o power (vddq) be from the same power source and brought up simultaneously . if separate power sources are used, vdd must lead vddq . 2 . once power supply voltages are stable and the cke has been driven high, it is safe to apply the clock . 3 . once the clock is stable, a 200 s (minimum) delay is required by the mobile ddr sdram prior to applying an executable command . during this time, nop or deselect commands must be issued on the command bus . 4 . issue a precharge all command . 5 . issue nop or deselect commands for at least trp time . 6 . issue an auto refresh command followed by nop or deselect commands for at least trfc time . issue a second auto refresh command followed by nop or deselect commands for at least trfc time . as part of the individualization sequence, two auto refresh commands must be issued . typically, both of these commands are issued at this stage as described above . 7 . using the load mode register command, load the standard mode register as desired . 8 . issue nop or deselect commands for at least tmrd time . 9 . using the load mode register command, load the extended mode register to the desired operating modes . note that the order in which the standard and extended mode registers are programmed is not critical . 10 . issue nop or deselect commands for at least tmrd time . 11 . the mobile ddr sdram has been properly initialized and is ready to receive any valid command . functional description
is43lr32800g, is46lr32800g 11 rev. a | november 2013 www.issi.com - dram@issi.com notes: 1. p cg = precharge command, mrs = load mode register command, ar ef = autorefresh command, act = active command, ra = row address, ba = bank address. 2. nop or deselect commands are required for at least 200s. 3. other valid commands are possible. 4. nops or deselects are required during this time. 5. two clocks at minimum. figure 7 : power up sequence act ba ba 0 = l , ba 1 = h ba 0 = l , ba 1 = l all banks mrs mrs ar ef ar ef pcg nop nop 2 nop 3 c l k / c l k cke t 0 c ommand 1 t 1 ta 0 tcl dm a0~a9, a11 tb 0 tc 0 td 0 te 0 tf 0 tck lvcmos high level a 10 ba 0 , ba 1 dqs , dq high - z t = 200 s tis ra code code tis tih ra code code tis tih tis tih trp 4 trfc 4 trfc 4 tmrd 4,5 tmrd 4,5 tih vddq vdd tis tih load standard mode register load extended mode register power - up : vdd and c l k stable don t care
is43lr32800g, is46lr32800g 12 rev. a | november 2013 www.issi.com - dram@issi.com mode register the mode register is used to define the specific mode of operation of the mobile ddr sdram . this definition includes the selection of a burst length, a burst type, a cas latency . the mode register is programmed via the load mode register command and will retain the stored information until programmed again, the device goes into deep power - down mode, or the device loses power . mode register bits a 0 - a 2 specify the burst length, a 3 specifies the type of burst (sequential or interleaved), a 4 - a 6 specify the cas latency, and a 7 - a 12 should be set to zero . ba 0 and ba 1 must be zero to access the mode register . the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation . violating either of these requirements will result in unspecified operation . burst length read and write accesses to the mobile ddr sdram are burst oriented, with the burst length being programmable, as shown in figure (mode register set definition) . the burst length determines the maximum number of column locations that can be accessed for a given read or write command . burst lengths of 2 , 4 , 8 or 16 are available for both the sequential and the interleaved burst types . reserved states should not be used, as unknown operation or incompatibility with future versions may result . when a read or write command is issued, a block of columns equal to the burst length is effectively selected . all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached . the block is uniquely selected by a 1 - a 8 when the burst length is set to two ; by a 2 - a 8 when the burst length is set to four ; by a 3 - a 8 when the burst length is set to eight ; and by a 4 - a 8 when the burst length is set to sixteen . the remaining (least significant) address bit(s) is (are) used to select the starting location within the block . the programmed burst length applies to both read and write bursts . cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data . the latency can be set to 2 , 3 clocks, as shown in figure (standard mode register definition) . for cl = 3 , if the read command is registered at clock edge n, then the data will be available at (n + 2 clocks + tac) . for cl = 2 , if the read command is registered at clock edge n, then the data will be available at (n + 1 clock + tac) . figure 8 : cas latency (bl=4) / c k c k c ommand t 0 t 1 t 2 t 3 t 1 n t 2 n t 3 n read nop nop nop dqs dq tac cl = 3 d out n + 1 trpre 2 tck t 4 t 4 n nop trpst d out n d out n + 2 d out n + 3 don t care dqs dq tac cl = 2 d out n + 1 trpre 1 tck trpst d out n d out n + 2 d out n + 3 l l
is43lr32800g, is46lr32800g 13 rev. a | november 2013 www.issi.com - dram@issi.com extended mode register the extended mode register controls the functions beyond those controlled by the mode register . these additional functions are special features of the mobile ddr sdram . they include partial array self refresh (pasr) and driver strength (ds) . the extended mode register is programmed via the mode register set command (ba 0 = 0 , ba 1 = 1 ) and retains the stored information until programmed again, the device goes into deep power - down mode, or the device loses power . the extended mode register must be programmed with a 8 through a 11 set to 0 . the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation . violating either of these requirements results in unspecified operation . partial array self refresh for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh . the refresh options are as follows : ? full array : banks 0 , 1 , 2 , and 3 ? half array : banks 0 and 1 ? quarter array : bank 0 ? one eighth array : half of bank 0 ? one sixteenth array : quarter of bank 0 write and read commands can still occur during standard operation, but only the selected banks will be refreshed during self refresh . data in banks that are disabled will be lost . output driver strength because the mobile ddr sdram is designed for use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available . drive strength should be selected based on the expected loading of the memory bus . bits a 5 and a 6 of the extended mode register can be used to select the driver strength of the dq outputs . there are four allowable settings for the output drivers . temperature compensated self refresh in the mobile ddr sdram, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device . temperature compensated self refresh allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile sdram device . this allows great power savings during self refresh during most operating temperature ranges . only during extreme temperatures would the controller have to select a tcsr level that will guarantee data during self refresh . every cell in the dram requires refreshing due to the capacitor losing its charge over time . the refresh rate is dependent on temperature . at higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often . historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected . thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures . this temperature compensated refresh rate will save power when the dram is operating at normal temperatures . it is not supported for any temperature grade with t a above + 85 c .
is43lr32800g, is46lr32800g 14 rev. a | november 2013 www.issi.com - dram@issi.com commands the following commands truth table and dm operation truth table provide quick reference of available commands. this is follo wed by a written description of each command. d eselect the deselect function ( / cs high) prevents new commands from being executed by the mobile ddr sdram. the mobile ddr sdram is effectively deselected. operations already in progress are not affected. no o peration (nop) the no operation (nop) command is used to instruct the selected ddr sdram to perform a nop ( / cs = low, / ras = / cas = / we = high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. a ctive the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0 C a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. r ead the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0 C a 8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. w rite the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0 - a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. p recharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( trp ) after the precharge command is issued. except in the case of concurrent auto precharge , where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. input a10 determines whether one or all banks are to be precharged , and in the case where only one bank is to be precharged , inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as dont care. once a bank has been precharged , it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging .
is43lr32800g, is46lr32800g 15 rev. a | november 2013 www.issi.com - dram@issi.com auto precharge auto precharge is a feature which performs the same individual - bank precharge function described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. this earliest valid stage is determined as if an explicit precharge command was issued at the earliest possible time, without violating tras (min) . the user must not issue another command to the same bank until the precharge time ( trp ) is completed. b urst t erminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated. the open page which the read burst was terminated from remai ns open. a uto refresh auto refresh is used during normal operation of the mobile ddr sdram and is analogous to / cas - before - / ras (cbr) refresh in fpm/edo drams. this command is nonpersistent , so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a dont care during an auto refresh command. the 256mb mobile ddr sdram requires auto refresh cycles at an average interval of t refi (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. although not a jedec requirement, to provide for future functionality features, cke must be active (high) during the auto ref res h period. the auto refresh period begins when the auto refresh command is registered and ends trfc later. s elf refresh the self refresh command can be used to retain data in the mobile ddr sdram, even if the rest of the system is powered down. wh en in the self refresh mode, the mobile ddr sdram retains data without external clocking. the self refresh command is initiated lik e an auto refresh command except cke is disabled (low). all command and address input signals except cke are dont care during sel f refresh. during self refresh, the device is refreshed as identified in the external mode register (see pasr setting). for a the full a rra y refresh, all four banks are refreshed simultaneously with the refresh frequency set by an internal self refresh oscillator. this oscillat or changes due to the temperature sensors input. as the case temperature of the mobile ddr sdram increases, the oscillation frequency will cha nge to accommodate the change of temperature. this happens because the dram capacitors lose charge faster at higher temperatures. t o e nsure efficient power dissipation during self refresh, the oscillator will change to refresh at the slowest rate possible to mainta in the devices data. the procedure for exiting self refresh requires a sequence of commands. first, c lock must be stable prior to cke going back high. once cke is high, the mobile ddr sdram must have nop commands issued for txsr is required for the completion of any internal refresh in progress. the self refresh command is not applicable for operation with t a > 85 o c. deep power - down deep power down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of th e devices. data in the array and in the mode and extended mode registers will not be retained once the device enters deep power do wn mode. this mode is entered by having all banks idle then /cs and /we held low with /ras and /cas held high at the rising edge of th e c lock, while cke is low. this mode is exited by asserting cke high. after applying nop commands for 200 s, the power up and initialization sequence must be followed . this mode is not applicable for operation with t a > 85 o c.
is43lr32800g, is46lr32800g 16 rev. a | november 2013 www.issi.com - dram@issi.com s10 s9 s8 refresh multipliers 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 2x 1 0 0 1x 1 0 1 reserved 1 1 0 0.25x 1 1 1 reserved s3 s2 s1 s0 manufacturer id 1 0 1 1 issi all others other manufacturers data bus (dq) dq0 dq1 dq2 dq3 dq4 dq5 dq7 dq9 figure9 : status register read (srr) 31~16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved density dt dw refresh multiplier revision id manufacturer mode register ( sx ) status register read the status register read (srr) command allows the user to access the manfacturer device information. it is optional for the user. the 16 - bit encoded data is stored in the status register, and can be output onto dq0~dq15, with a fixed burst length (bl) of 2. the ma nufacturer's id is on s0~s3, the device revision id is on s4~s7, the refresh rate is on s8~s10, the data width is on s11, the device type is on s12, and the density is on s13~s15. the register bit range s16~s31 is reserved. the srr command sequence is as follows: ? all banks must be idle, and reads and writes completed ? a mode register set (mrs) command is issued with ba0=1, ba1=0, and a0~a11=0 to initiate srr ? after a time period tsrr , a read command is issued to any bank or address ? the next valid command may be issued a time period tsrc after the read command the read command causes the status register data to be output after two or three clock cycles, whichever corresponds to the c as latency setting. in the first half of the read burst, the dq16~dq31 values are dont care, and in the second half of the read burs t, the dq0~dq31 values are "don't care. dq6 dq8 dq10 dq11 dq12 dq13 dq14 dq15 s11 device width 0 x16 1 x32 s12 device type 0 mddr 1 lpddr2 s15 s14 s13 density 0 0 0 128mb 0 0 1 256mb 0 1 0 512mb 0 1 1 1gb 1 0 0 2gb 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved dq31~dq16
is43lr32800g, is46lr32800g 17 rev. a | november 2013 www.issi.com - dram@issi.com note: 1. all states and sequences not shown are illegal or reserved. 2. deslect and nop are functionally interchangeable. 3. autoprecharge is non - persistent. a10 high enables autoprecharge , while a10 low disables autoprecharge 4. burst terminate applies to only read bursts with autoprecharge disabled. this command is undefined and should not be used for read with autoprecharge enabled, and for write bursts. 5. this command is burst terminate if cke is high and deep power down entry if cke is low. 6. if a10 is low, bank address determines which bank is to be precharged . if a10 is high, all banks are precharged and ba0 - ba1 are don t care. 7. this command is auto refresh if cke is high, and self refresh if cke is low. 8. all address inputs and i/o are ''don't care'' except for cke. internal refresh counters control bank and row addressing. 9. all banks must be precharged before issuing an auto - refresh or self refresh command. 10. ba0 and ba1 value select among mode register set (mrs), extended mode register (emrs) or status register read (srr). 11. used to mask write data, provided coincident with the corresponding data. 12. cke is high for all commands shown except self refresh and deep power - down. function /cs /ras /cas /we ba a10/ap addr note deselect (nop) h x x x x x x 2 no operation (nop) l h h h x x x 2 active (select bank and activate row) l l h h v row row read (select bank and column and start read burst) l h l h v l col re a d with ap (read burst with auto recharge) l h l h v h col 3 write (select bank and column and start write burst) l h l l v l col write with ap (write burst with auto recharge) l h l l v h col 3 burst terminate or enter deep power down l h h l x x x 4,5 precharge (deactivate row in selected bank) l l h l v l x 6 precharge all (deactivate rows in all banks) l l h l x h x 6 auto refresh or enter self refresh l l l h x x x 7,8,9 mode register set l l l l v op_code 10 function dm dq note write enable l valid 11 write inhibit h x 11 table5 : dm truth table table4: command truth table
is43lr32800g, is46lr32800g 18 rev. a | november 2013 www.issi.com - dram@issi.com note: 1. cken is the logic state of cke at clock edge n ; cke n - 1 was the state of cke at the previous clock edge. 2. current state is the state of mobile ddr immediately prior to clock edge n . 3. commandn is the command registered at clock edge n, and action n is the result of command n . 4. all states and sequences not shown are illegal or reserved. 5. deselect and nop are functionally interchangeable. 6. power down exit time (txp) should elapse before a command other than nop or deselect is issued. 7. self refresh exit time (txsr) should elapse before a command other than nop or deselect is issued. 8. the deep power - down exit procedure must be followed as discussed in the deep power - down section of the functional description. 9. the clock must toggle at least one time during the txp period. 10. the clock must toggle at least once during the txsr time. see the other truth tables h h enter deep power down burst terminate all banks idle l h self refresh entry auto refresh all banks idle l h 5 active power down entry nop or deselect bank(s) active l h 5 precharge power down entry nop or deselect all banks idle l h 5,8 exit deep power down nop or deselect deep power down h l 5,7,10 exit self refresh nop or deselect self refresh h l 5,6,9 exit power down nop or deselect power down h l maintain deep power down x deep power down l l maintain self refresh x self refresh l l maintain power down x power down l l note action n command n current state cken cken - 1 table6 : cke truth table
is43lr32800g, is46lr32800g 19 rev. a | november 2013 www.issi.com - dram@issi.com note: 1. the table applies when both cken - 1 and cken are high, and after txsr or txp has been met if the previous state was self refre sh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for prechar gin g. 5. a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled. 6. the new read or write command could be auto precharge enabled or auto precharge disabled. 7. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 8. the following states must not be interrupted by a command issued to the same bank. deselect or nop commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table3, and according to truth table 4. ? precharging: starts with the registration of a precharge command and ends when trp is met. once trp is met, the bank will be in the idle state. ? row activating: starts with registration of an active command and ends when trcd is met. once trcd is met, the bank will be in the ''row active'' state. ? read with ap enabled: starts with the registration of the read command with auto precharge enabled and ends when trp has been met. once trp has been met, the bank will be in the idle state. ? write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when trp has been met. once trp is met, the bank will be in the idle state. table7 : c urrent state bank n truth table (command to bank n ) current state command action note /cs /ras /cas /we description any h x x x deselect(nop) continue previous operation l h h h nop continue previous operation idle l l h h active select and activate row l l l h auto refresh auto refresh 10 l l l l mode register set mode register set 10 l l h h precharge no action if bank is idle row active l h l h read select column & start read burst l h l l write select column & start write burst l l h l precharge deactivate row in bank (or banks) 4 read (without auto recharge) l h l h read truncate read & start new read burst 5,6 l h l l write truncate read & start new write burst 5,6,13 l l h l precharge truncate read, start precharge l h h l burst terminate burst terminate 11 write (without auto precharge) l h l h read truncate write & start new read burst 5,6,12 l h l l write truncate write & start new write burst 5,6 l l h l precharge truncate write, start precharge 12
is43lr32800g, is46lr32800g 20 rev. a | november 2013 www.issi.com - dram@issi.com 9. the following states must not be interrupted by any executable command; deselect or nop commands must be applied to each positive clock edge during these states. ? refreshing: starts with registration of an auto refresh command and ends when trfc is met. once trfc is met, the mobile ddr will be in an ''all banks idle'' state. ? accessing mode register: starts with registration of a mode register set command and ends when tmrd has been met. once tmrd is met, the mobile ddr will be in an ''all banks idle'' state. ? precharging all: starts with the registration of a precharge all command and ends when trp is met. once trp is met, the bank will be in the idle state. 10. not bank - specific; requires that all banks are idle and no bursts are in progress. 11. not bank - specific. burst terminate affects the most recent read burst, regardless of bank. 12. requires appropriate dm masking. 13. a write command may be applied after the completion of the read burst; otherwise, a burst terminate must be used to end t he read prior to asserting a write command.
is43lr32800g, is46lr32800g 21 rev. a | november 2013 www.issi.com - dram@issi.com table8 : current state bank n truth table (command to bank m ) current state command action note /cs /ras /cas /we description any h x x x deselect(nop) continue previous operation l h h h nop continue previous operation idle x x x x any any command allowed to bank m row activating, active, or precharging l l h h active activate row l h l h read start read burst 8 l h l l write start write burst 8 l l h l precharge precharge read with auto precha rge disabled l l h h active activate row l h l h read state read burst 8 l h l l write start write burst 8,10 l l h l precharge precharge write with auto precharge disabled l l h h active activate row l h l h read start read burst 8,9 l h l l write start write burst 8 l l h l precharge precharge read with auto precharge l l h h active activate row l h l h read start read burst 5,8 l h l l write start write burst 5,8,10 l l h l precharge precharge write with auto precharge l l h h active activate row l h l h read start read burst 5,8 l h l l write start write burst 5,8 l l h l precharge precharge
is43lr32800g, is46lr32800g 22 rev. a | november 2013 www.issi.com - dram@issi.com note: 1. the table applies when both cke n - 1 and cke n are high, and after txsr or txp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 5. read with ap enabled and write with ap enabled: the read with autoprecharge enabled or write with autoprecharge enabled states can be broken into two parts: the access period and the precharge period. for read with ap, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all the data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr measured as if auto precharge was disable d. the access period starts with registration of the command and ends where the precharge period (or trp) begins. during the precharge period, of the read with autoprecharge enabled or write with autoprecharge enabled states, active, precharge, read, and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other banks may be applied. in either case, all other related limitations apply (e.g. contention between read data and write data must be avoided). 6. auto refresh, self refresh, and mode register set commands may only be issued when all bank are idle. 7. a burst terminate command cannot be issued to another bank; i t applies to the bank represented by the current state only. 8. reads or writes listed in the command column include reads and writes with auto precharge enabled and reads and writes with auto precharge disabled. 9. requires appropriate dm masking. 10. a write command may be applied after the completion of data output, otherwise a burst terminate command must be issued to end the read prior to asserting a write command.
is43lr32800g, is46lr32800g 23 rev. a | november 2013 www.issi.com - dram@issi.com table9 : absolute maximum rating parameter symbol rating unit storage temperature t stg - 55 ~ 150 ? c voltage on any pin relative to vss v in , v out - 0.3 ~ 2.7 v voltage on vdd relative to vss vdd, vddq - 0.3 ~ 2.7 v short circuit output current i os 50 ma power dissipation p d 0.7 w note : stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect reliability . table10 : operating temperature parameter symbol min typ max unit note power supply voltage vdd 1.7 1.8 1.9 5 v power supply voltage vddq 1.7 1.8 1.9 5 v 2 input high voltage v ih (dc) 0. 7 x vddq vddq + 0.3 v input low voltage v il (dc) - 0.3 0. 3 x vddq v input differential voltage, for ck, /ck inputs v id (dc) 0.4 x vddq vddq + 0.6 v 3 o utput high voltage v oh (dc) 0.9 x vddq - v i oh = - 0.1ma o utput low voltage v ol (dc) - 0.1 x vddq v i ol =0.1ma input leakage current i li - 2 2 ua output leakage current i lo - 5 5 ua input high voltage , all inputs v ih (ac) 0. 8 x vddq vddq + 0.3 v input low voltage , all inputs v il (ac) - 0.3 0. 2 x vddq v input differential voltage, for c k, /ck inputs v id (ac) 0.6 x vddq vddq + 0.6 v 3 input differential crosspoint voltage for ck and /ck inputs v ix (ac) 0. 4 x vddq 0. 6 x vddq v 4 table11 : ac/dc operating conditions (1) note s : 1. all voltages are referenced to vss = 0v 2. vdd and vddq must track each other, and vddq must not exceed the level of vdd. 3. the magnitude of difference between input level on ck and input level on /ck. 4. the value of v ix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. parameter symbol rating unit ambient temperature (automotive, a2) t a - 40 ~ 105 ? c ambient temperature (automotive, a1) - 40 ~ 85 ambient temperature (industrial) - 40 ~ 85 ambient temperature (commercial) 0 ~ 70
is43lr32800g, is46lr32800g 24 rev. a | november 2013 www.issi.com - dram@issi.com table13 : ac operating test condition parameter symbol value unit ac input high/low level voltage v ih / v il 0. 8 x vddq / 0.2 x vddq v input timing measurement reference level voltage v trip 0.5 x vddq v input rise / fall time t r / t f 1 / 1 ns output timing measurement reference level voltage v outref 0.5 x vddq v output load capacitance for access time measurement c l 20 pf figure10 : output load circuit table12 : capacitance (t a =25 ? c, f=1mhz, vdd= 1.8 v) parameter pin symbol min max unit input capacitance ck, /ck c i1 1.5 7.0 pf a0~a12, ba0~ba1, cke, /cs, /ras, /cas, /we c i2 1.5 6.0 pf dm0~dm3 c i3 2 4.5 pf data & dqs input/output capacitance dq0~dq31, dqs0~dqs3 c io 2 4.5 pf table14 : ac overshoot/undershoot specification figure11 : ac overshoot/undershoot definition 10.6k ? 13.9k ? vddq 20pf output 20pf 50 ? vtt=0.5 x vddq z0=50 ? dc output load circuit ac output load circuit parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v maximum overshoot area above vdd/vddq 3v - ns maximum undershoot area below vss/vssq 3v - ns maximum amplitude vdd/vddq vss/vssq voltage [v] maximum amplitude time [ns] overshoot area undershoot area
is43lr32800g, is46lr32800g 25 rev. a | november 2013 www.issi.com - dram@issi.com table15b : dc characteristic (dc operating conditions unless otherwise noted) note : 1. measured with outputs open 2. refresh period is 64ms, applicable for t a < 85 ? c 3. all values applicable for application with t a < 85 ? c 4. typical value at room temperature parameter symbol test condition speed unit note - 5 - 6 - 75 operating one bank active - precharge current idd 0 trc = trc(min) , tck = tck(min) , cke is high , /cs is high between valid commands , address inputs are switching , data bus inputs are stable 70 60 55 ma 1 precharge power - down standby current idd2p a ll bank s idle, cke is low , /cs is high, tck = tck(min) , a ddress and control i nputs are switching , data bus inputs are stable 300 ? a precharge power - down standby current with clock stop idd2ps a ll banks idle, cke is low , /cs is high, ck = low, /ck = high , a ddress and control inputs are switching , data bus inputs are stable 300 ? a precharge non power - down standby current idd2n a ll banks idle, cke is high , / cs is high, tck = tck(min) , address and control inputs are switching , data bus inputs are stable 10 ma precharge non power - down standby current with clock stop idd2ns a ll banks idle, cke is high , / cs is high, ck = low, /ck = high , a ddress and control inputs are switching , data bus inputs are stable 4 ma active power - down standby current idd3p o ne bank active, cke is low , /cs is high, tck = tck(min) , a ddress and control inputs are switching , data bus inputs are stable 1 ma active power - down standby current with clock stop idd3ps on e bank active, cke is low , /cs is high, ck = low , /ck = high , a ddress and control inputs are switching , data bus inputs are stable 1 ma active non power - down standby current idd3n o ne bank active , cke is high , / cs is high, tck = tck(min) , a ddress and control inputs are switching , data bus inputs are stable 20 ma active non power - down standby current with clock stop idd3ns o ne bank active , cke is high , / cs is high, ck = low, / ck = high , a ddress and control inputs are switching , data bus inputs are stable 10 ma operating burst read current idd4r o ne bank active , bl=4 , cl=3 , tck = tck(min) , continuous read bursts , iout=0ma , address inputs are switching , 50% data change each burst transfer 140 130 120 ma 1 operating burst write c urrent idd4w o ne bank active , bl=4 , tck=tck(min) , continuous write bursts , address inputs are switching , 50% data change each burst transfer 60 55 50 ma 1 auto refresh current idd5 trc=trfc(min) , tck=tck(min) , burst refresh , cke is high , a ddress and control inputs are switching , data bus inputs are stable 100 ma 2 self refresh current pasr tcsr idd6 cke is low ck=low, / ck=high tck=tck(min) extended mode register set to all 0's , address and control inputs are stable , data bus inputs are stable u a 4 banks 85 ? c 400 45 ? c 350 2 banks 85 ? c 380 45 ? c 340 1 bank 85 ? c 360 45 ? c 330 half bank 85 ? c 340 45 ? c 310 quarter bank 85 ? c 320 45 ? c 300 standby current in deep power down mode idd8 a ddress and control inputs are stable , data bus inputs are stable 10 ua 4
is43lr32800g, is46lr32800g 26 rev. a | november 2013 www.issi.com - dram@issi.com parameter symbol - 5 unit note min max system clock cycle t ime c l =3 tck 5 1000 ns 1 cl=2 10 ns 1 dq output a ccess t ime from c k, /ck cl=3 tac 2.0 5.0 ns cl=2 2.0 8.0 clock high pulse w idth tch 0.45 0.55 tck clock low pulse w idth tcl 0.45 0.55 tck cke min. p ulse w idth (high / low pulse width) tcke 1 tck dq and dm input setup t ime tds 0.48 ns 2, 3, 4 dq and dm input hold t ime tdh 0.48 ns 2, 3, 4 dq and dm input p ulse width tdipw 1.6 ns 5 address and control input setup t ime tis 0.9 ns 4, 6, 7 address and control input hold t ime tih 0.9 ns 4, 6, 7 address and control input pulse width tipw 2.3 ns 5 dq & dqs low - impedance time from ck, / ck tlz 1.0 ns 8 dq & dqs high - impedance time from ck, / ck t h z 5.0 ns 8 dqs - dq skew tdqsq 0.4 ns 9 half clock period thp tch , tcl ns data hold skew factor tqhs 0.5 ns dq / dqs o utput h old time from dqs tqh thp - tqhs ns write command to first dqs latching transition tdqss 0.75 1.25 tck dqs input high pulse width tdqsh 0.35 0.6 tck dqs input low pulse width tdqsl 0.35 0.6 tck dqs falling edge to ck setup time tdss 0.2 tck dqs falling edge hold time from ck tdsh 0.2 tck access window of dqs from ck, /ck cl=3 tdqsck 2.0 5.0 ns cl=2 2.0 8.0 ns active to precharge command period tras 40 ns active to active command period trc 55 ns mode register set command cycle time tmrd 2 tck srr to read tsrr 2 tck read of srr to next valid command tsrc cl+1 tck refresh period tref 64 ms 15 average periodic refresh interval trefi 15.6 us 10,15 auto refresh period trfc 70 ns active to read or write delay trcd 15 ns precharge command period trp 15 ns a ctive bank a to active bank b delay trrd 10 ns w rite recovery t ime twr 15 ns auto precharge write recovery + precharge t ime tdal ( twr / tck ) + ( trp / tck ) internal write to read command delay twtr 1 tck dqs read preamble cl=3 trpre 0.9 1.1 tck 11 cl=2 0.5 1.1 tck 11 dqs read postamble trpst 0.4 0.6 tck dqs write preamble twpre 0.25 tck dqs write preamble setup time twpres 0 ns 12 dqs write postamble twpst 0.4 0.6 tck 13 exit power down to next valid command delay txp 1 tck 14 self refresh exit to next valid command delay txsr 120 ns table16: ac characteristic (ac operation conditions unless otherwise noted)
is43lr32800g, is46lr32800g 27 rev. a | november 2013 www.issi.com - dram@issi.com parameter symbol - 6 - 75 unit note min max min max system clock cycle t ime c l =3 tck 6 1000 7.5 1000 ns 1 cl=2 10 10 ns 1 dq output a ccess t ime from c k, /ck cl=3 tac 2.0 5.5 2.0 6.0 ns cl=2 2.0 8.0 2.0 8.0 clock high pulse w idth tch 0.45 0.55 0.45 0.55 tck clock low pulse w idth tcl 0.45 0.55 0.45 0.55 tck cke min. p ulse w idth (high / low pulse width) tcke 1 1 tck dq and dm input setup t ime tds 0.6 0.9 ns 2, 3, 4 dq and dm input hold t ime tdh 0.6 0.9 ns 2, 3, 4 dq and dm input p ulse width tdipw 1.8 2.0 ns 5 address and control input setup t ime tis 1.0 1.3 ns 4, 6, 7 address and control input hold t ime tih 1.0 1.3 ns 4, 6, 7 address and control input pulse width tipw 2.7 3.0 ns 5 dq & dqs low - impedance time from ck, / ck tlz 1.0 1.0 ns 8 dq & dqs high - impedance time from ck, / ck t h z 5 .5 6 ns 8 dqs - dq skew tdqsq 0.5 0.6 ns 9 half clock period thp tch, tcl tch, tcl ns data hold skew factor tqhs 0.65 0.75 ns dq / dqs o utput h old time from dqs tqh thp - tqhs thp - tqhs ns write command to first dqs latching transition tdqss 0.75 1.25 0.75 1.25 tck dqs input high pulse width tdqsh 0. 35 0.6 0.4 0.6 tck dqs input low pulse width tdqsl 0. 35 0.6 0.4 0.6 tck dqs falling edge to ck setup time tdss 0.2 0.2 tck dqs falling edge hold time from ck tdsh 0.2 0.2 tck access window of dqs from ck, /ck cl=3 tdqsck 2.0 5.5 2.0 6.0 ns cl=2 2.0 8.0 2.0 8.0 ns active to precharge command period tras 42 45 ns active to active command period trc 60 75 ns mode register set command cycle time tmrd 2 2 tck srr to read tsrr 2 2 tck read of srr to next valid command tsrc cl+1 cl+1 tck refresh period tref 64 64 ms 15 average periodic refresh interval trefi 15.6 15.6 us 10,15 auto refresh period trfc 70 70 ns active to read or write delay trcd 18 22.5 ns precharge command period trp 18 22.5 ns a ctive bank a to active bank b delay trrd 12 15 ns w rite recovery t ime twr 15 15 ns auto precharge write recovery + precharge t ime tdal ( twr / tck ) + ( trp / tck ) internal write to read command delay twtr 1 1 tck dqs read preamble cl=3 trpre 0.9 1.1 0.9 1.1 tck 11 cl=2 0.5 1.1 0.5 1.1 tck 11 dqs read postamble trpst 0.4 0.6 0.4 0.6 tck dqs write preamble twpre 0.25 0.25 tck dqs write preamble setup time twpres 0 0 ns 12 dqs write postamble twpst 0.4 0.6 0.4 0.6 tck 13 exit power down to next valid command delay txp 1 1 tck 14 self refresh exit to next valid command delay txsr 120 120 ns table16: ac characteristic (ac operation conditions unless otherwise noted)
is43lr32800g, is46lr32800g 28 rev. a | november 2013 www.issi.com - dram@issi.com note : 1 . the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for th e clock pin) during access or precharge states (read, write, including tdpl , and precharge commands). cke may be used to reduce the data rate. 2 . the transition time for dq, dm and dqs inputs is measured between vil(dc) to vih(ac) for rising input signals, and vih(dc) to vil(ac) for falling input signals. 3 . dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. 4 . input slew rate 0.5v/ns and < 1.0v/ns. 5 . these parameters guarantee device timing but they are not necessarily tested on each device. 6 . the transition time for address and command inputs is measured between vih and vil. 7 . a ck , /ck slew rate must be 1.0 v/ns ( 2.0v/ns if measured differentially) is assumed for this parameter. 8 . thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 9 . tdqsq consists of data pin skew and output pattern effects, and p - channel to n - channel variation of the output drivers for any given cycle. 1 0 . a maximum of eight refresh commands can be posted to any given low - power ddr sdram, meaning that the maximum absolute interval between any refresh command and the next refresh command is 8 * trefi . 1 1 . a low level on dqs may be maintained during high - z states (dqs drivers disabled) by adding a weak pull - down element in the system. it is recommended to turn off the weak pull - down element during read and write bursts (dqs drivers enabled). 1 2 . the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a v alid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previous ly in progress on the bus, dqs will be transitioning from hi - z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss . 1 3 . the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, bu t s ystem performance (bus turnaround) will degrade accordingly. 14. at least one clock pulse is required during t xp . 15. the specifications in the table for t ref and t refi are applicable for all temperature grades with t a < +85 ? c. only a2 temperature grade supports operation with t a > 85 ? c, and these values must be further constrained with t ref max of 32ms, and t refi max of 7.8s . input setup/hold slew rate [v/ns] ?tds/?tis [ps] ?tdh/?tih [ps] 1.0 0 0 0.5 +150 +150 ck,/ck setup/hold slew rate [v/ns] ?tds/?tis [ps] ?tdh/?tih [ps] 1.0 0 0
is43lr32800g, is46lr32800g 29 rev. a | november 2013 www.issi.com - dram@issi.com timing diagram bank/row activation the active command is used to activate a row in particular bank for a subsequent read or write access . the value of the ba 0 ,ba 1 inputs selects the bank, and the address provided on a 0 - a 12 (or the highest address bit) selects the row . before any read or write commands can be issued to a bank within the mobile ddr sdram, a row in that bank must be opened . this is accomplished via the active command, which selects both the bank and the row to be activated . the row remains active until a precharge (or read with auto precharge or write with auto precharge) command is issued to the bank . a precharge (or read with auto precharge or write with auto precharge) command must be issued before opening a different row in the same bank . figure 12: trcd, trrd, trc once a row is open(with an active command) a read or write command may be issued to that row, subject to the trcd specification . trcd(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered . a subsequent active command to a different row in the same bank can only be issued after the previous active row has been closed(precharge) . the minimum time interval between successive active commands to the same bank is defined by trc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row - access overhead . the minimum time interval between successive active commands to different banks is defined by trrd . figure 11 : active command notes : 1 . ra : row address 2 . ba : bank address c l k / c l k cke / cs / ras / cas / we ra ba a 0 ~ a 11 ba 0 , ba 1 don t care rd / wt with ap act nop nop nop bank a row act nop / clk c l k c ommand t 0 t 1 t 2 t 3 a 0 - a 12 ba 0 , ba 1 col bank a t 4 t a 0 t a 1 t rcd don t care row bank b t rrd bank a row act t rc t a 2 tch tcl tis tih tc k
is43lr32800g, is46lr32800g 30 rev. a | november 2013 www.issi.com - dram@issi.com read the read command is used to initiate a burst read to an active row . the value of ba 0 and ba 1 selects the bank and address inputs select the starting column location . the value of a 10 determines whether or not auto - precharge is used . if auto - precharge is selected, the row being accessed will be precharged at the end of the read burst ; if auto precharge is not selected, the row will remain open for subsequent access . the valid data - out elements will be available cas latency after the read command is issued . the mobile ddr drives the dqs during read operations . the initial low state of the dqs is known as the read preamble and the last data - out element is coincident with the read postamble . dqs is edge - aligned with read data . upon completion of a burst, assuming no new read commands have been initiated, the i/o's will go high - z . figure 13 : read command notes : 1 . ca : column address 2 . ba : bank address 3 . a 10 =high : enable auto precharge a 10 =low : disable auto precharge figure 14 : read data out timing (bl=4) notes: 1. bl=4 2. shown with nominal tac, tdqsck and tdqsq c l k / c l k cke / cs / ras / cas / we ca a 0 ~ a 8 a 10 ba ba 0 , ba 1 don t care bank a col n / c l k c l k c ommand t 0 t 1 t 2 t 3 t 1 n t 2 n t 3 n read nop nop nop dqs dq cl = 3 d out n + 1 trpre t 4 t 4 n nop trpst d out n d out n + 2 d out n + 3 don t care address tac tdqsck tqh tlz thz tdqsq dqs dq cl = 2 d out n + 1 d out n d out n + 2 d out n + 3 trpre tac trpst
is43lr32800g, is46lr32800g 31 rev. a | november 2013 www.issi.com - dram@issi.com figure 15 : consecutive read bursts (bl=4) figure 16 : non - consecutive read bursts (bl=4) notes: 1. dout n or m = data - out from column n or m 2. bl=4,8,16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first) 3 . shown with nominal tac, tdqsck and tdqsq notes: 1. dout n or m = data - out from column n or m 2. bl=4,8,16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first) 3 . shown with nominal tac, tdqsck and tdqsq d out m bank a col m bank a col n nop read nop nop nop read t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dq cl = 3 command dqs don t care d out n + 1 d out n d out n + 2 d out n + 3 d out m + 1 bank a col m bank a col n nop read nop nop nop read t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dq cl = 3 command dqs don t care d out n + 1 d out n d out n + 2 d out n + 3 cl = 3 nop d out m d out m + 1
is43lr32800g, is46lr32800g 32 rev. a | november 2013 www.issi.com - dram@issi.com figure 18 : read burst terminate (bl=4,8 or 16) truncated reads data from any read burst may be truncated with a burst terminate command, as shown in figure16. the burst terminate latency is equal to the read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read comman d, where x equals the number of desired data element pairs (pairs are required by the 2n - prefetch architecture). data from any read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used. a read burst may be followed by, or truncated with, a precharge command to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the n - prefetch architecture). this is shown in figure (read to precharge). following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. figure 17 : random read access notes: 1. dout n or m,p,q = data - out from column n or m,p,q 2. bl=2,4,8,16 (if 4,8 or 16, the following burst interrupts the previous) 3. reads are to an active row in any bank. 4 . shown with nominal tac, tdqsck and tdqsq notes: 1. dout n = data - out from column n 2. cke=high 3 . shown with nominal tac, tdqsck and tdqsq bank a col m bank a col p d out p bank a col q bank a col n read read read nop nop read t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dq cl = 3 command dqs don t care d out n + 1 d out n d out m d out m + 1 nop d out q d out q + 1 d out p + 1 bank a col n nop read bst nop nop t 0 t 1 t 2 t 3 a ddress t 4 / clk clk dq cl = 3 command dqs don t care d out n + 1 d out n
is43lr32800g, is46lr32800g 33 rev. a | november 2013 www.issi.com - dram@issi.com figure 20 : read to precharge (bl=4) figure 19 : read to write terminate (bl=4,8 or 16) notes: 1. dout n = data - out from column n , din m = data - in from column m. 2. cke=high 3 . shown with nominal tac, tdqsck and tdqsq notes: 1. dout n = data - out from column n. 2. read to precharge equals 2 tck, which allows 2 data pairs of data - out. 3 . shown with nominal tac, tdqsck and tdqsq bank a col m nop bank a col n nop read bst write nop t 0 t 1 t 2 t 3 a ddress t 4 / clk clk dq cl = 3 command dqs don t care d out n + 1 d out n tdqss ( nom ) d in m d in m + 1 t 5 bank a ( a , or all ) bank a col n pcg read nop act nop nop t 0 t 1 t 2 t 3 address t 4 t 5 / clk clk dq cl = 3 command dqs bank a row trp don t care d out n + 1 d out n d out n + 2 d out n + 3
is43lr32800g, is46lr32800g 34 rev. a | november 2013 www.issi.com - dram@issi.com figure 22 : write burst (bl=4) write the write command is used to initiate a burst write access to an active row. the value of ba0, ba1 selects the bank and addre s s inputs select the starting column location. the value of a10 determines whether or not auto precharge is used.if autoprecharge is selected, the row being accessed will b e precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. inp ut data appearing on the data bus, is written to the memory array subject to the dm input logic level appearing coincident with the d ata . if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high, the c orr esponding data - inputs will be ignored, and a write will not be executed to that byte/column location. the memory controller drives the dqs during write operations. the initial low state of the dqs is known as the write preamble and the low state following the last data - in e lement is write postamble. upon completion of a burst, assuming no new commands have been initiated, the i/o's will stay high - z and any addition al input data will be ignored. figure 21 : write command notes : 1 . ca : column address 2 . ba : bank address 3 . a 10 =high : enable auto precharge a 10 =low : disable auto precharge notes: 1. din n = data - in from column n. c l k / c l k cke / cs / ras / cas / we ca a 0 ~ a 8 a 10 ba ba 0 , ba 1 don t care bank a col m bank a col n write nop write / c l k c l k t 0 t 1 t 2 t 3 t 1 n t 2 n dq tdqss twpst don t care dqs twpres twpre tdh tds d m d in n d in n + 1 d in n + 2 d in n + 3 a ddress command tdqsh
is43lr32800g, is46lr32800g 35 rev. a | november 2013 www.issi.com - dram@issi.com figure 23 : consecutive write to write (bl=4) figure 24 : non - consecutive write to write (bl=4) notes: 1. din n = data - in from column n. 2. each write command may be to any banks. notes: 1. din n = data - in from column n. 2. each write command may be to any banks. write write nop nop nop nop bank a col n d in m bank a col m t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in n + 2 d in n + 3 d in m + 1 d in m + 2 d in m + 3 don t care nop write nop nop write nop bank a col n d in m t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in n + 2 d in n + 3 d in m + 1 d in m + 2 d in m + 3 don t care bank a col m tdqss ( nom ) nop
is43lr32800g, is46lr32800g 36 rev. a | november 2013 www.issi.com - dram@issi.com figure 25 : random write to write figure 26 : write to read (uninterrupting) notes: 1. din n,p,m,q = data - in from column n,p,m,q. 2. each write command may be to any banks. notes: 1. din n = data - in from column n, dout m = data - out from column m. 2. twtr is referenced from the first positive ck edge after the last data - in pair. 3. read and write command can be directed to different banks, in which case twtr is not required and the read command could be applied ealier. d in q + 1 bank a col q bank a col p write write write write nop bank a col n d in m bank a col m t 0 t 1 t 2 t 3 a ddress t 4 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in p d in p + 1 d in m + 1 d in q don t care nop write bank a col m nop nop read nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in n + 2 d in n + 3 don t care cl = 3 nop nop d out m + 1 d out m t wtr d out m + 2 t 6 t 7
is43lr32800g, is46lr32800g 37 rev. a | november 2013 www.issi.com - dram@issi.com figure 27 : write to read (interrupting) figure 28 : write to read (odd number of data interrupting) notes: 1. din n = data - in from column n, dout m = data - out from column m. 2. twtr is referenced from the first positive ck edge after the last data - in pair. notes: 1. din n = data - in from column n, dout m = data - out from column m. 2. twtr is referenced from the first positive ck edge after the last data - in pair. write nop t 6 t 7 nop nop read nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 don t care bank a col m cl = 3 nop nop d out m + 1 d out m d out m + 2 d out m + 3 t wtr t 6 t 7 t 0 t 1 t 2 t 3 t 4 t 5 dqs dq tdqss ( nom ) dm d in n don t care cl = 3 d out m + 1 d out m d out m + 2 d out m + 3 t wtr write nop nop nop read nop bank a col n a ddress / clk clk command bank a col m nop nop
is43lr32800g, is46lr32800g 38 rev. a | november 2013 www.issi.com - dram@issi.com figure 29 : write to precharge (uninterrupting) figure 30 : write to precharge (interrupting) notes: 1. din n = data - in from column n. 2. twr is referenced from the first positive ck edge after the last data - in pair. 3. read and write command can be directed to different banks, in which case twr is not required and the read command could be applied ealier. notes: 1. din n = data - in from column n. 2. twr is referenced from the first positive ck edge after the last data - in pair. 3. read and write command can be directed to different banks, in which case twr is not required and the read command could be applied ealier. pcg nop write nop nop nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in n + 2 d in n + 3 don t care twr nop write nop nop pcg nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 twr don t care
is43lr32800g, is46lr32800g 39 rev. a | november 2013 www.issi.com - dram@issi.com figure 31 : write to precharge (odd number of data interrupting) notes: 1. din n = data - in from column n. 2. twr is referenced from the first positive ck edge after the last data - in pair. 3. read and write command can be directed to different banks, in which case twr is not required and the read command could be applied ealier. don t care nop write nop nop pcg nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n twr
is43lr32800g, is46lr32800g 40 rev. a | november 2013 www.issi.com - dram@issi.com precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks . the banks will be available for subsequent row access some specified time (trp) after the precharge command issued . input a 10 determines whether one or all banks are to be precharged . in the case where only one bank is to be precharged (a 10 =low), inputs ba 0 ,ba 1 select the banks . when all banks are to be precharged (a 10 =high), inputs ba 0 ,ba 1 are treated as a dont care . once a bank has been precharged, it is in the idle state and must be actived prior to any read or write commands being issued to that bank . figure 32 : precharge command notes : 1 . ba : bank address mode register the mode register contains the specific mode of operation of the mobile ddr sdram. this register includes the selection of a burst length ( 2, 4, 8, 16), a cas latency(2, 3), a burst type. the mode register set must be done before any activate command after the power up sequence. any contents of the mode register be altered by re - programming the mode register through the execution of mode register set command. t ck 2 ck min 0 1 2 3 4 5 6 7 8 / clk clk 9 10 c md t rp precharge all bank mode resister set command (any) figure 33 : mode resister set c l k / c l k cke / cs / ras / cas / we ba a 10 ba 0 , ba 1 don t care
is43lr32800g, is46lr32800g 41 rev. a | november 2013 www.issi.com - dram@issi.com figure 35 : self refresh self refresh this state retains data in the mobile ddr, even if the rest of the system is powered down (even without external clocking). n o te refresh interval timing while in self refresh mode is scheduled internally in the mobile ddr and may vary and may not meet trefi time . " don't care" except cke, which must remain low. an internal refresh cycle is scheduled on self refresh entry. the procedure for exit ing self refresh mode requires a series of commands. first clock must be stable before cke going high. nop commands should be issued f or the duration of the refresh exit time (txsr), because time is required for the completion of any internal refresh in progress. th e u se of self refresh mode introduces the possibility that an internally timed event can be missed when cke is raised for exit from self re fre sh mode. figure 34 : auto refresh auto refresh the auto refresh command is used during normal operation of the mobile ddr. it is non persistent, so must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. the mobile ddr requires auto refresh com man ds at an average periodic interval of trefi. to allow for improved efficiency in scheduling and switching between tasks, some flexibil ity in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to any given mobile ddr, and th e maximum absolute interval between any auto refresh command and the next auto refresh command is 8*trefi. aref nop nop nop aref pcg nop / c l k c l k cke t 0 c ommand t 1 t 3 tch tcl dqs , dq , dm tb 0 tis tih a 10 tc k t 2 t 4 ta 0 trp don t care valid all banks one bank ba ba 0 , ba 1 act nop tb 0 ra ta 2 ba ra nop valid trfc trfc tis tih valid nop aref nop / c l k c l k cke t 0 c ommand t 1 t a 0 dqs , dq , dm tb 0 tis tih t a 1 trp don t care address txsr tis tih tis tis valid self - refresh mode entry self - refresh mode exit a0~a9, a11
is43lr32800g, is46lr32800g 42 rev. a | november 2013 www.issi.com - dram@issi.com figure 36 : power down (active or precharge) figure 37 : deep power down power down power down occurs if cke is set low coincident with device deselect or nop command and when no accesses are in progress. if p ower down occurs when all banks are idle, it is precharge power down. if power down occurs when one or more banks are active, it i s r eferred to as active power down. the device cannot stay in this mode for longer than the refresh requirements of the device, without los ing data. the power down state is exited by setting cke high while issuing a device deselect or nop command. a valid command can be issued aft er txp. deep power down the deep power - down (dpd) mode enables very low standby currents. all internal voltage generators inside the mobile ddr are st opped and all memory data is lost in this mode. all the information in the mode register and the extended mode register is lost. ne xt figure, deep power - down command shows the deep power - down command all banks must be in idle state with no activity on the data bus prior to entering the dpd mode. while in this state, cke must be held in a constant low state. to exit the dpd mode, cke is taken high af ter the clock is stable and nop command must be maintained for at least 200 us. valid nop nop valid / c l k c l k cke t 0 c ommand t 1 ta 0 tch tcl dqs , dq , dm tis tih valid address tc k valid tis tis tih tis tih t 2 ta 1 tb 0 must not exceed refresh device limits don t care power - down mode entry power - down mode exit t xp valid nop nop dpd nop / c l k c l k cke t 0 c ommand t 1 ta 0 dqs , dq , dm tb 0 address tc ke valid tis t 2 ta 1 ta 2 don t care deep power - down mode entry deep power - down mode exit t = 200 us
is43lr32800g, is46lr32800g 43 rev. a | november 2013 www.issi.com - dram@issi.com clock stop mode clock stop mode is a feature supported by mobile ddr sdram devices. it reduces clock - related power consumption during idle periods of the device. conditions: the mobile ddr sdram supports clock stop in case: ? the last access command (active, read, write, precharge, auto refresh or mode register set) has executed to completion, including any data - out during read bursts; the number of required clock pulses per access command depends on the device's ac timing parameters and the clock frequency; ? the related timing condition (trcd, twr, trp, trfc, tmrd) has been met; ? cke is held high. when all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be entered with ck held low and /ck held high. clock stop mode is exited when the clock is restarted. nops command have to be issued for at least one clock cycle before the next access command may be applied. additional clock pulses might be required depending on the system characteristics . figure 37 illustrates the clock stop mode: ? initially the device is in clock stop mode; ? the clock is restarted with the rising edge of t0 and a nop on the command inputs; ? with t1 a valid access command is latched; this command is followed by nop commands in order to allow for clock stop as soon as this access command has completed; ? t n is the last clock pulse required by the access command latched with t1. ? the timing condition of this access command is met with the completion of t n ; therefore tn is the last clock pulse required by this command and the clock is then stopped. figure 38 : clock stop mode dq ,dqs ( high C z ) exit clock stop mode enter clock stop mode vail command cke t0 t1 t2 t n / clk clk a dd timing condition cmd clock stopped dont care nop cmd nop nop nop valide high
is43lr32800g, is46lr32800g 44 rev. a | november 2013 www.issi.com - dram@issi.com notes: 1. p cg = precharge command, srr = status register read command, act = active command, ra = row address, ba = bank address. 2. other valid commands are possible. 3. nops or deselects are required during this time. 4. d out 1 = data out, d out 2 = dummy data. 5. data output occurs 3 cycles after read for cl3, or 2 cycles after read for cl2. figure 39 : status register read nop 3 nop 3 nop 3 read nop 3 srr nop pcg act 2 c l k / c l k cke c ommand 1 tcl dq a0~a9, a11 tck a 10 ba 0 , ba 1 dqs high z tsrr tsrc tis tih don t care 0 0 ra ra ba d out 4 ba0=h ba1=l cl=3 d out2+1
is43lr32800g, is46lr32800g 45 rev. a | november 2013 www.issi.com - dram@issi.com configuration frequency (mhz) speed (ns) order part no. package 8mx32 200 5 is43lr32800g - 5bl 90 - ball bga, lead - free 166 6 is43lr32800g - 6bl 90 - ball bga, lead - free ordering information C vdd = 1.8v commercial range: (0 o c to +70 o c) configuration frequency (mhz) speed (ns) order part no. package 8mx32 200 5 is43lr32800g - 5bli 90 - ball bga, lead - free 166 6 is43lr32800g - 6bli 90 - ball bga, lead - free industrial range: ( - 40 o c to +85 o c) configuration frequency (mhz) speed (ns) order part no. package 8mx32 200 5 is46lr32800g - 5bla1 90 - ball bga, lead - free 166 6 is46lr32800g - 6bla1 90 - ball bga, lead - free automotive range, a1: ( - 40 o c to +85 o c) configuration frequency (mhz) speed (ns) order part no. package 8mx32 200 5 is46lr32800g - 5bla2 90 - ball bga, lead - free 166 6 is46lr32800g - 6bla2 90 - ball bga, lead - free automotive range, a2: ( - 40 o c to +105 o c) note: the - 6 speed option supports - 75 timing specifications
is43lr32800g, is46lr32800g 46 rev. a | november 2013 www.issi.com - dram@issi.com
is43lr32800g, is46lr32800g 47 rev. a | november 2013 www.issi.com - dram@issi.com

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